`include "C:\Users\lenovo\Desktop\Files\Linear_RISCV\LR_ver_0\src\include\include.vh"
module 	imm_all_gen(
    input       [31:0]           instr,
    output  reg [31:0]      imm_I_type,
    output  reg [31:0]      imm_S_type,
    output  reg [31:0]      imm_B_type,
    output  reg [31:0]      imm_J_type_L,
    output  reg [31:0]      imm_J_type_R,
    output  reg [31:0]      imm_U_type
);         wire [4:0]       zimm;
        assign zimm = instr[19:15];
        wire    [6:0]     opcode_i;
        assign opcode_i = instr[6:0];
        always @(*) begin //I type imm;
                case (instr[14:12])
                    `INST_RV32I_SLLI     :imm_I_type = {27'b0, instr[24:20]}; 
                    `INST_RV32I_SRLI_SRAI:imm_I_type = {27'b0, instr[24:20]}; 
                    default              :
                        imm_I_type = (opcode_i==`INST_RV32I_OPCODE_CSR)?{instr[14]?{27'b0,zimm}:32'b0}:{{20{instr[31]}}, instr[31:20]};                                                        
                endcase
        end
        always @(*) begin //S&B&J&U type imm
            imm_S_type   = {{20{instr[31]}} , instr[31:25], instr[11:7]};
            imm_B_type   = {{20{instr[31]}} , instr[7]    , instr[30:25], instr[11:8] , 1'b0};
            imm_J_type_L = {{12{instr[31]}} , instr[19:12], instr[20]   , instr[30:21], 1'b0};
            imm_J_type_R = {{20{instr[31]}} , instr[31:20] };
            imm_U_type   = {    instr[31:12], 12'b0};
        end

endmodule